Synplify Pro Reviews Software And IP
What is Synopsys Synplify. The new features in the 2010.09 release. (Nasdaq: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, today announced the availability of enhancements to its Synplify Pro® and Synplify® Premier FPGA synthesis tools. Synopsys Enhances Synplify FPGA Synthesis Software With up to 4X Faster Runtime and New Team-Design Capabilities: Synopsys, Inc.
Consequently, setting the correct goals in the Synplify Pro tool is an essential consideration with regard to obtaining the best results. Indeed, the Synplify Pro tool is timing-driven, which means that it simultaneously optimizes for area and performance, but it stops as soon as the timing constraints are met. Synplify premier user guide, cp physics web review chapter14 light, novell certified linux professional study guide emmett.Setting up your design correctly can result in huge performance increases or reduction in area (cost). Design Advisory: A special class of Xilinx Answer Record designed to keep you up to date on critical known issues, and help guide your designs around them.Synplify premier user guide. This paper describes four preferred ways to set up your design and four methods of fine-tuning synthesis, all of which can be used together or independently.Search Support: You can refine your results easily by narrowing your search by document type, answer record type, products, design flow, and more.
This ensures that critical paths are squeezed as much as possible (see the discussions on Route constraint later in this tutorial for more information). For maximum performance, ensure that there is 10-15% negative slack on each critical clock. Do not over-constrain by more than 15%.
The tool then calculates the minimum setup time between the clocks in this case 10ns.Warning: If the clocks are completely unrelated, it may require several clock periods before the clocks match up again. The Synplify software rolls the clocks forward until they match up again. Instead, define all clocks in a constraint file (.sdc) and ensure that unrelated clocks are set in separate clock groups (when clocks are in the same group, the Synplify Pro tool works out the worst-case setup time for the clock-to-clock paths).Example: A timing diagram for two clocks that are in the same clock group is presented in Fig 1.
Although it may seem to be counter-intuitive, defining exceptions that are not the most critical paths can actually speed-up the design.Example: The Synplify Pro tool performs timing-driven tristate-to-mux conversion. With this information, the tool can ignore these paths and concentrate on the real critical paths. If the setup time is too short, it is best to re-constrain the clocks so as to ensure that they are more related.(Click this image to view a larger, more detailed version)Provide all timing exceptions, such as false and multicycle paths, to the Synplify Pro tool. You can check the setup time in the Clock Relationships table in the log file ( Fig 2 ).
This means that it is very important to define the I/O standard in the constraint file (.sdc), thereby ensuring that the Synplify Pro tool can apply the correct timing model to the I/O pads.Include all Clearboxes or timing models for black boxesIf Clearbox files or models are provided, the Synplify Pro tool knows the path timing and can alter the logic surrounding the boxes based on the timing constraints. Finally, I/O pad delays can vary substantially for different I/O standards. It is also recommended that you check that the “Use clock period for unconstrained I/O” implementation option is disabled, as this generates a default constraint for every I/O in the design. Thus, it is important to accurately constrain I/O delays (and also to avoid any over-constraining). In these situations, applying a multicycle constraint to the tristate path causes the Synplify Pro tool to keep the tbuf elements, thus saving area.I/O paths are often timing-critical because of the large delays through the I/O pads. Usually data on buses is not critical and can survive a few clock cycles as the bus master has to wait.
Not all designs benefit from enabling these features. Following these guidelines will usually save a device size or a speed grade and – in many cases – both.The following optimization techniques are design-dependent. If Clearbox models are unavailable, provide the Synplify Pro tool with both the input and output timing constraints of the black box.Fine-tuning designs to improve timing or areaOnce a design is set up using the methods described above and has subsequently been synthesized, there are additional options you can use to improve design performance or area.
It also re-encodes the FSMs based upon the number of states:It is recommended that you enable this option. However, if the critical path goes through arithmetic operators, no resource sharing will be performed.FSM Compiler: This option extracts and optimizes FSMs. It is recommended that you first enable this option as it should provide maximum performance and minimum area. Retiming attributes such as syn_allow_retiming let you refine your constraints by enabling or disabling retiming on specific registers.Resource Sharing: : With this option enabled, the software performs timing-driven sharing of hardware resources such as adders and subtractors.
Multiplier – syn_multstyle The no_rw_check qualifier (used in conjunction with a memory type) deserves a special mention: when inferring a memory, the Synplify Pro tool will often add the necessary glue logic to resolve a read-write conflict (same address) in order to exactly match the functionality described in the RTL. You can force the tool to use a specific resource implementation by adding any of the following attributes: You can configure macro blocks within the Synplify Pro tool based on the design requirements. There are some cases where you don't want logic placed, say, in RAM or DSP MAC block. Resource allocationThe use of dedicated macro blocks usually provides the best area solution, but routing delays to and from these blocks can degrade performance. It is recommended to leave this option disabled, but if you turn it on you will see FSMs in the critical path.
The following attributes and directives are the most commonly used.” It is thus highly recommended that you use this feature as much as possible.Optimization controls The Synplify Pro tool provides directives and attributes to shape and control logic according to your design requirements. Additionally, note that some memory coding styles (for example, dual-clock dual-port memory with registered output) cannot be mapped into memory blocks unless the no_rw_check qualifier is specified. By specifying no_rw_check , this glue logic will not be inserted, resulting in a faster and smaller design.
Disables sequential optimizations on registers, preventing removal, merging, inverter push-through, and FSM extraction. syn_preserve (in source code). It is also useful for timing exceptions, because you can apply a –thru constraint to it. Preserves an RTL net throughout synthesis and prevents ALM packing and replication.
This control is a hard limit on modules and instances but a soft limit when it is set globally. Controls the maximum fanout limit, triggering register replication and buffering. syn_maxfan (in constraint file). Prevents replication of registers.
syn_use_ioff (in constraint file). Useful for high-fanout clock-enable nets that are timing-critical. Forces a connection to the enable pin of the register additional logic is moved to the D input path.
Aligning the routing delays almost always results in far better results. The –route switch allows you to align synthesis estimates with the place and route delays. It can provide a +10% performance improvement with minimal effort.If the Synplify Pro timing estimate is different from the Place and Route value, the difference will prevent the Synplify Pro tool from optimizing the real critical paths. Useful for improving performance based on the critical path.The –route constraint is probably the most important, but least known timing constraint.
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